This is the thing I find *really* frustrating .... the SPD spec has some pretty
diagrams
that explain the read and write operations ... and Figure 10 on page 10 of 28 appears
to line up with line line 70 of 350 of this morning's northsouthbridge/sis/630/ipl.S
Intel: EEPROM Sequential Read Operation: address "1 0 1 0 A2 A1 A0 1"
SIS: movw $0x04a1, %ax # SPD is on SMBUS Address 1010 xyz1
# where xyz are
DIMM Slot Number
Cool ... but where does it say, anywhere in the SPD Spec, that the SPD address scheme
has *anything* to do with either the SMBus or the I2C ??
Where are you guys getting this missing information? There seems to be something
underlying that threads these standards together, that I just can't find / touch ... ??
Like poking the PCI bus for certain functions ... and poking the SMBus for certain
functions ... just so frustrating ... its like trying to program in windows.
----- Original Message -----
>From: "Ollie Lho" <[EMAIL PROTECTED]>
>To: "Ian" <[EMAIL PROTECTED]>
>Subject: Re: memory and stuffs
>Date: Thu, 21 Feb 2002 17:06:01 +0800
>
> Ian wrote:
>
> > Anyway, I set about getting ram running using hacked around code (cleaned up
mostly)
> > from the ALi code used in the CUA ipl.S ... which went pretty smoothly until I got
>bogged
> > down for 6hours ... only recently concluding that the reason why my RAM won't init
> > is because I have SDRAM not DRAM (*argh!*) ... which brings me to the sweet looking
> > chunk of code in the 630 ipl.S ....
> >
>
>
> You should start from 630 ipl.S first.
>
> > .. I still don't grasp these relationships well ... but the SPD info ... is it
>always going to be
> > at the same address on the SMBus or is that vendor/implementation dependant .. ?
> >
>
>
> Did you read the SPD spec ?? IT can be found on intel's web site.
>
>
> P.S. If you can not find the spec, I can send you a copy.
>
> Ollie
>
>
