I appreciate your help learning this... Reads come from ROM, writes to RAM. Just like my old C64.
XBCX bit 2 can be turned on to make it *write* to BIOS socket, as well as read. I see now in the 430TX northbridge can be told intercept reads and/or writes to memory areas including BIOS. Thanks again! Jeremy ----- Original Message ----- From: "Ronald G Minnich" <[EMAIL PROTECTED]> To: "Jeremy Jackson" <[EMAIL PROTECTED]> Cc: <[EMAIL PROTECTED]> Sent: Wednesday, March 27, 2002 9:32 PM Subject: Re: important changes .... > On Wed, 27 Mar 2002, Jeremy Jackson wrote: > > > Ok put another way: 0xf000 - 0xffff from who's > > point of view, CPU, PCI bus, or ISA bus? > > real mode physical address from the CPU, after reset. > > > > Ok... I see ipl.S for sis630 does a far call right at the > > reset_vector: so the i386 switches from the dummy > > segment descriptor it gets at reset 0xfffff000 to > > 0xfe00. > > yes. at reset is is in "special mode". That first jump pops it into real > mode and you can only address the first 1M. So the flash and DoC have to > be addressed at 0xf0000. > > > Sorry kinda thinking outloud here. I think the > > PIIX4 makes 0xf000-0xffff ram, which the > > std BIOS shadows itsself into before jumping > > there, but I'm just guessing. What does the 630 do? > > no, what you do on the PIIX4 is this: > - enable the "write to ram" feature for the BIOS area. This means that > writes to 0xf0000 (for example) go to RAM, reads go to XBUS. > - bcopy 0xf0000 to 0xf0000 (not a typo). > - enable the "read from ram" feature for the BIOS area. This means that > reads to 0xf0000 go to ram. Your BIOS is now ram-based. > > ron >
