On 24 Apr 2002 11:34:59 -0400, Christopher Stutts wrote: >It would be nice if someone actually had instructions on setting up a >chipset instead of just reverse engineering things. Intel doesn't >document what you need to do, although it has posted some binaries for >use in embedded BX systems. (And our hw guys have trouble getting info >out of Intel even after signing nondisclosures.) I've got a 440BX >going, but apparently you don't initialize a 430TX the same way.
You mean publicly document? My NDA docs have the exact instructions right down to what and where. My only trouble with docs from Intel so far has been knowing what to ask my FAE for. Usually I have him submit a question to intel tech and the answer comes back that its documented in such and such manual. Then I request it. Well actually I take that partially back.. The documentation for the eepro100 sucks meat. Its very out of date with respect to thier latest flavors of the chip. >1. For my BX BIOS, and for the commericial BIOS I ran though the ICE, >multiple dram rows (must?) get initialized simultaneously. For every >SDRAM command issued by reading address n, address next_row_boundary+n >also gets read. For the TX, commercial BIOS and LinuxBIOS (must?) do >one row at a time. I'm afraid I can't comment. >5. For reliable BX/memtest86 operation, misc drive strength settings had >to be just so. Mere SDRAM fill/verify did not reveal any errors. >Fortunately the TX doesn't have these settings. Are you running a 100Mhz fsb? If so then the drive strengths are very important. We found this out with our last design or perhaps I should say mis-design. -- Richard A. Smith Bitworks, Inc. [EMAIL PROTECTED] 501.846.5777 x204 Sr. Design Engineer http://www.bitworks.com
