Texas Instruments TMS1000

Introduction

The TMS1000 is actually a series of 4-bit microprocessors produced by Texas Instruments. The units are actally microcontrollers containing ROM, RAM, I/O, & CPU on one chip. The following table summarizes the differences between the units.

TMS1000 Microcontroller feature summary
	1000	1200	1070	1270	1100	1300
	TMS
Pkg Pin Count	28	40	28	40	28	40
ROM Program Bytes	1024	1024	1024	1024	2048	2048
RAM Data Nibble	64	64	64	64	128	128
R Signal Outputs	11	13	11	13	11	16
O Data Outputs	8	8	8	10	8	8

General Description

The block diagram of the cpu (inside the dotted line).

[image of TMS1000 logical block diagram]

With the TMS1000 series, what you see is all you get. The units are not capable of expansion in any way. The highest clock frequency attainable by the series is 0.4MHz. this results in a 2.5 microsecond clock cycle. All instructions execute in 6 clock cycles. The devices were fabricated using PMOS and required a single -15V supply.

Register Description

The register mapping is as follows: [image of TMS1000 register layout]

NOTE: The X register is two bits wide on the devices with 64 nibbles of RAM and three bits wide on the 128 nibble RAM units. The accumulator is standard type, aside from being four bits wide. The concatenated X and Y registers become a six or seven bit data register. This creates a pointer into the 64 or 128 nibbles of RAM. The concatenated Page Address Register and Program Counter constitute a ten bit program counter. On the devices with 2048 bytes of program memory, there is a 1 bit "Chapter Flag" used as the most significant bit of an eleven bit program counter. The Y register can also be used as a secondary accumulator and an output address register. The Subroutine Return Register and Page Buffer Register are storage areas that implement a one level subroutine call mechanism. When a subroutine is called, the contents of the Page Address Register and the Page Buffer Register are swapped. The Program Counter is copied to the Subroutine Return Register. The subroutine target address is then moved to the Program Counter.

Addressing Modes

The TMS1000 series microcontrollers have separate program and data memories. All data is accessed via implied addressing. The X and Y registers become the data pointer. Only subroutine calls and branch instructions address program memory. The call instruction (discussed earlier) as well as the branch instruction loads the Program Counter. if the branch occurs inside of a subroutine, the Page Address register will not be affected. However, outside of a subroutine, the Page Address register will be loaded with the contents of the Page Buffer register.

Flags

There is only one flag. This status flag serves as a carry status. All branch and subroutine call instructions are conditional. The unique aspect of this flag is that it's passive state is a logic one. If an operation resets the flag, it will return to a logic one after one instruction cycle (six clock cycles). What this means for the programmer is that instructions that modify the status flag must be immediately followed by the instruction that tests the flag.

I/O

The only data input available is through the 4 bit K input lines. Input instructions collect whatever signals are available on the input lines at the time. Output data exist as 8 O lines and 11, 13, or 16 control, or R lines. The accumulator and the status flag determine the bit pattern of the O lines. This information has to be requested when the chip is produced. What this means is that only 32 distinct patterns can be generated by the O lines. The Y register determines which individual R control line is being set or reset.

Pin Diagrams

[pin diagram of TMS1200] [pin diagram of TMS1270] [pin diagram of TMS1300]

Note that The R and O outputs are resposible for the additional pins on the 1200,1270, and 1300 chips. All of these units have internal clock logic which can be connected to an RC circuit with one end of the capacitor connected to Vss, one end of the resistor connected to Vdd and the opposite ends of the components connected to both OSC1 and OSC2. If an externally generated signal is to be used, it must be connected to OSC1 while OSC2 is grounded. A design utilizing many clocked chips would benefit from this setup.

The INIT (reset signal) should be held high for at least 6 clock cycles after power is applied. Reset causes the Page Address and Page Buffer registers to be loaded with binary ones. The O and R outputs as well as the program counter are zeroed. A consequence of this is that upon reset, the first instruction executed is at hex location 3C0.

Instruction Information

All instructions generate one byte of object code. Moreover, all instructions execute in one macine (6 clock) cycle. The following link lists the instructions available on the TMS1000 series. Note that this table has an extra column to specify which instructions are only available on certain chips.