Segher Boessenkool wrote: >> The CPU15 erratum on MPC8xx chips can cause incorrect code execution >> under certain circumstances, where there is a conditional or indirect >> branch in the last word of a page, with a target in the last cache line >> of the next page. This patch implements one of the suggested >> workarounds, by forcing a TLB miss whenever execution crosses a page >> boundary. This is done by invalidating the pages before and after the >> one being loaded into the TLB in the ITLB miss handler. > > > So you never found a bug workaround without the terrible > overhead of this one? A shame :-(
The only lower-overhead workaround I know of requires compiler modifications (and I made it configurable to allow for that possibility). -Scott _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
