>>> Well, I had already checked with Ben, who wrote the code, and my >>> understanding is that the reads are intended to work around some >>> misbehaving Apple bridges, >> >> None of the PCI interfaces on the U3 or U4 bridges have that >> problem as far as I know. I think the workaround was copied >> from code for older Apple bridges? > > Okay, then the change should be fine for maple.
Yes. Of course, as usual, testing is needed, yada yada. >>> but that a sync after the write (implied by >>> releasing pci_lock in the generic pci code) should suffice for those. >> >> I don't see how a sync could help here at all, not more than >> an eieio anyway? > > Alright, well, maybe take it up with Ben when I post the patch for > powermac, since that's where it could actually matter. It should be fine on PowerMac as well -- all G5s use U3/U4, the workaround is for certain older Apple bridge chips. Segher _______________________________________________ Linuxppc-dev mailing list [email protected] https://ozlabs.org/mailman/listinfo/linuxppc-dev
