On Tue, Dec 13, 2016 at 04:54:30PM -0600, Segher Boessenkool wrote: > On Tue, Dec 13, 2016 at 09:39:55PM +0100, christophe leroy wrote: > > Le 13/12/2016 à 20:15, Segher Boessenkool a écrit : > > >On Tue, Dec 13, 2016 at 07:19:41PM +0100, Christophe Leroy wrote: > > >>At exception prologs, once SRR0 and SRR1 have been saved, MSR RI is > > >>set to mark the interrupt as recoverable. > > >> > > >>MSR RI has to be unset before writing into SRR0 and SRR1 at exception > > >>epilogs. > > > > > >Why? What goes wrong without this? Etc. > > > > The following patch implements perf instruction counting using the 8xx > > debug counters. When the counter reaches 0, it fires a debug exception. > > If that exception happens between the setting of srr0/srr1 and the rfi, > > values set to srr0/srr1 are lost and we end up with an Oops. > > > > To avoid that, MSR RI has to be unset. That way, because the debug > > counters mode is set to masked mode in register LCTRL2, no debug > > interrupt will happen during that critical phase. > > Okay, so why then do you do an expensive sequence on all other processors? >
Does ppc32 support runtime code patching? If so, you could perhaps utilize that to only inflict the painful code sequence when perf is enabled.