On Thu, 2017-02-09 at 08:28 +0530, Aneesh Kumar K.V wrote: > In the kernel we do follow the below sequence in different code paths. > pte = ptep_get_clear(ptep) > .... > set_pte_at(ptep, pte) > > We do that for mremap, autonuma protection update and softdirty clearing. This > implies our optimization to skip a tlb flush when clearing a pte update is > not valid, because for DD1 system that followup set_pte_at will be done witout > doing the required tlbflush. Fix that by always doing the dd1 style pte update > irrespective of new_pte value. In a later patch we will optimize the > application > exit case. > > Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> > Signed-off-by: Aneesh Kumar K.V <aneesh.ku...@linux.vnet.ibm.com>
Tested-by: Michael Neuling <mi...@neuling.org> > --- > arch/powerpc/include/asm/book3s/64/radix.h | 12 +++--------- > 1 file changed, 3 insertions(+), 9 deletions(-) > > diff --git a/arch/powerpc/include/asm/book3s/64/radix.h > b/arch/powerpc/include/asm/book3s/64/radix.h > index b4d1302387a3..70a3cdcdbe47 100644 > --- a/arch/powerpc/include/asm/book3s/64/radix.h > +++ b/arch/powerpc/include/asm/book3s/64/radix.h > @@ -144,16 +144,10 @@ static inline unsigned long radix__pte_update(struct > mm_struct *mm, > * new value of pte > */ > new_pte = (old_pte | set) & ~clr; > - /* > - * If we are trying to clear the pte, we can skip > - * the below sequence and batch the tlb flush. The > - * tlb flush batching is done by mmu gather code > - */ > - if (new_pte) { > - asm volatile("ptesync" : : : "memory"); > - radix__flush_tlb_pte_p9_dd1(old_pte, mm, addr); > + asm volatile("ptesync" : : : "memory"); > + radix__flush_tlb_pte_p9_dd1(old_pte, mm, addr); > + if (new_pte) > __radix_pte_update(ptep, 0, new_pte); > - } > } else > old_pte = __radix_pte_update(ptep, clr, set); > asm volatile("ptesync" : : : "memory");