On 02/20/2017 07:12 PM, Michael Roth wrote: > With the inclusion of: > > powerpc/pseries: Implement indexed-count hotplug memory remove > powerpc/pseries: Implement indexed-count hotplug memory add > > we now have complete handling of the RTAS hotplug event format > as described by PAPR via ACR "PAPR Changes for Hotplug RTAS Events". > > This capability is indicated by byte 6, bit 5 of architecture > option vector 5, and allows for greater control over cpu/memory/pci > hot plug/unplug operations. > > Existing pseries kernels will utilize this capability based on the > existence of the /event-sources/hot-plug-events DT property, so we > only need to advertise it via CAS and do not need a corresponding > FW_FEATURE_* value to test for. > > Cc: Michael Ellerman <m...@ellerman.id.au> > Cc: Nathan Fontenot <nf...@linux.vnet.ibm.com> > Cc: David Gibson <da...@gibson.dropbear.id.au> > Signed-off-by: Michael Roth <mdr...@linux.vnet.ibm.com>
Reviewed-by: Nathan Fontenot <nf...@linux.vnet.ibm.com> > --- > arch/powerpc/include/asm/prom.h | 1 + > arch/powerpc/kernel/prom_init.c | 2 +- > 2 files changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/powerpc/include/asm/prom.h b/arch/powerpc/include/asm/prom.h > index 2c8001c..4a90634 100644 > --- a/arch/powerpc/include/asm/prom.h > +++ b/arch/powerpc/include/asm/prom.h > @@ -153,6 +153,7 @@ struct of_drconf_cell { > #define OV5_XCMO 0x0440 /* Page Coalescing */ > #define OV5_TYPE1_AFFINITY 0x0580 /* Type 1 NUMA affinity */ > #define OV5_PRRN 0x0540 /* Platform Resource Reassignment */ > +#define OV5_HP_EVT 0x0604 /* Hot Plug Event support */ > #define OV5_RESIZE_HPT 0x0601 /* Hash Page Table resizing */ > #define OV5_PFO_HW_RNG 0x1180 /* PFO Random Number Generator > */ > #define OV5_PFO_HW_842 0x1140 /* PFO Compression Accelerator > */ > diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c > index f3c8799..1a835e7 100644 > --- a/arch/powerpc/kernel/prom_init.c > +++ b/arch/powerpc/kernel/prom_init.c > @@ -839,7 +839,7 @@ struct ibm_arch_vec __cacheline_aligned > ibm_architecture_vec = { > 0, > #endif > .associativity = OV5_FEAT(OV5_TYPE1_AFFINITY) | > OV5_FEAT(OV5_PRRN), > - .bin_opts = OV5_FEAT(OV5_RESIZE_HPT), > + .bin_opts = OV5_FEAT(OV5_RESIZE_HPT) | OV5_FEAT(OV5_HP_EVT), > .micro_checkpoint = 0, > .reserved0 = 0, > .max_cpus = cpu_to_be32(NR_CPUS), /* number of cores > supported */ >