On Wed, Feb 22, 2017 at 03:43:59PM +1100, Alexey Kardashevskiy wrote: >The IODA2 specification says that a 64 DMA address cannot use top 4 bits >(3 are reserved and one is a "TVE select"); bottom page_shift bits >cannot be used for multilevel table addressing either. > >The existing IODA2 table allocation code aligns the minimum TCE table >size to PAGE_SIZE so in the case of 64K system pages and 4K IOMMU pages, >we have 64-4-12=48 bits. Since 64K page stores 8192 TCEs, i.e. needs >13 bits, the maximum number of levels is 48/13 = 3 so we physically >cannot address more and EEH happens on DMA accesses. > >This adds a check that too many levels were requested. > >It is still possible to have 5 levels in the case of 4K system page size. > >Signed-off-by: Alexey Kardashevskiy <a...@ozlabs.ru> >---
Acked-by: Gavin Shan <gws...@linux.vnet.ibm.com>