The patch resets the freeze counter on eeh_pe struct for PHB
associated with the cxl pci adapter. This would enable re-flashing of
the cxl-adapter beyond the default limit of 5.

Signed-off-by: Vaibhav Jain <vaib...@linux.vnet.ibm.com>
---
 drivers/misc/cxl/pci.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index 679afc9..3b14688 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -22,6 +22,7 @@
 #include <asm/pnv-pci.h>
 #include <asm/io.h>
 #include <asm/reg.h>
+#include <asm/eeh.h>
 
 #include "cxl.h"
 #include <misc/cxl.h>
@@ -1229,6 +1230,8 @@ static void cxl_pci_remove_afu(struct cxl_afu *afu)
 int cxl_pci_reset(struct cxl *adapter)
 {
        struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
+       struct eeh_dev *eehdev = pci_dev_to_eeh_dev(dev);
+       struct eeh_pe *devpe = eeh_dev_to_pe(eehdev);
        int rc;
 
        if (adapter->perst_same_image) {
@@ -1242,6 +1245,18 @@ int cxl_pci_reset(struct cxl *adapter)
        /* the adapter is about to be reset, so ignore errors */
        cxl_data_cache_flush(adapter);
 
+       /* If loading a new image, reset freeze counters for the PHB
+        * associated with the adapter.
+        */
+       if (devpe && adapter->perst_loads_image) {
+               /* Find the pe associated with the device PHB */
+               while (devpe->parent != NULL && (devpe->type & EEH_PE_PHB) == 0)
+                       devpe = devpe->parent;
+
+               dev_info(&dev->dev, "Resetting freeze counters for the PHB\n");
+               eeh_pe_reset_freeze_counter(devpe);
+       }
+
        /* pcie_warm_reset requests a fundamental pci reset which includes a
         * PERST assert/deassert.  PERST triggers a loading of the image
         * if "user" or "factory" is selected in sysfs */
-- 
2.9.3

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