On Tue, 28 Feb 2017 12:37:23 +0530 Mahesh Jagannath Salgaonkar <mah...@linux.vnet.ibm.com> wrote:
> On 02/28/2017 07:30 AM, Nicholas Piggin wrote: > > +long __machine_check_early_realmode_p9(struct pt_regs *regs) > > +{ > > + uint64_t nip, addr; > > + long handled; > > + struct mce_error_info mce_error_info = { 0 }; > > + > > + nip = regs->nip; > > + > > + if (P9_SRR1_MC_LOADSTORE(regs->msr)) { > > Asynch store errors are reported in the srr1 with codes srr1 42=1, 36=1, > 43=1 and 44:45 = 01 or 10. Since srr1 42=1, you may end up in > mce_handle_derror_p9() for asynch errors and look for error bits in > DSISR instead in SRR1. We will miss detecting asynch errors completely. After clarification from hardware, Asynch MCEs are reported with SRR1 bit 42 = 0, so I think this is okay. Thanks, Nick