Madhavan Srinivasan [ma...@linux.vnet.ibm.com] wrote:
> The LDST field and DATA_SRC in SIER identifies the memory hierarchy level
> (eg: L1, L2 etc), from which a data-cache miss for a marked instruction
> was satisfied. Use the 'perf_mem_data_src' object to export this
> hierarchy level to user space.
>
<snip>
> diff --git a/arch/powerpc/include/asm/perf_event_server.h
> b/arch/powerpc/include/asm/perf_event_server.h
> int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long
> *valp)
> {
> unsigned int unit, pmc, cache, ebb;
> diff --git a/arch/powerpc/perf/isa207-common.h
> b/arch/powerpc/perf/isa207-common.h
> index cf9bd8990159..982542cce991 100644
> --- a/arch/powerpc/perf/isa207-common.h
> +++ b/arch/powerpc/perf/isa207-common.h
> @@ -259,6 +259,19 @@
> #define MAX_ALT 2
> #define MAX_PMU_COUNTERS 6
>
> +#define ISA207_SIER_TYPE_SHIFT 15
> +#define ISA207_SIER_TYPE_MASK (0x7ull <<
> ISA207_SIER_TYPE_SHIFT)
> +
> +#define ISA207_SIER_LDST_SHIFT 1
> +#define ISA207_SIER_LDST_MASK (0x7ull <<
> ISA207_SIER_LDST_SHIFT)
> +
> +#define ISA207_SIER_DATA_SRC_SHIFT 53
> +#define ISA207_SIER_DATA_SRC_MASK (0x7ull << ISA207_SIER_DATA_SRC_SHIFT)
> +
> +#define P(a, b) PERF_MEM_S(a, b)
Madhavan, Peter,
Can we see if we can get the kernel to set 'perf_mem_data_src.val' in
endian-nuetral format?
With something like (untested) in include/uapi/linux/perf_event.h
#define PERF_MEM_OP_NBITS PERF_MEM_LVL_SHIFT
#define PERF_MEM_LVL_NBITS PERF_MEM_SNOOP_SHIFT
#define PERF_MEM_SNOOP_NBITS PERF_MEM_LOCK_SHIFT
#define PERF_MEM_TLB_NBITS PERF_MEM_TLB_SHIFT
and here in arch/powerpc/perf/isa207-common.h
#define PERF_MEM_S_BE_SHIFT(a) \
(63 - PERF_MEM_##a##_NBITS - PERF_MEM_##a##_SHIFT)
#define PERF_MEM_S_BE(a, s) \
(((__u64)PERF_MEM_##a##_##s) << PERF_MEM_S_BE_SHIFT(a))
#define P(a, b) PERF_MEM_S_BE(a, b)
Basically, have PERF_MEM_OP_NA be the right most bit and PERF_MEM_TLB_OS
the left most bit in perf_mem_data_src.val regardless of the endianness?
Sukadev
