Christophe Lombard <clomb...@linux.vnet.ibm.com> writes:
> The PSL initialization sequence has been updated to DD2.
> This patch adapts to the changes, retaining compatibility with DD1.
> The patch includes some changes to DD1 fix-ups as well.
>
> Tests performed on some of the old/new hardware.
>
> The function is_page_fault(), for POWER9, lists the Translation Checkout
> Responses where the page fault will be handled by copro_handle_mm_fault().
> This list is too restrictive and not necessary.
>
> This patches removes this restriction and all page faults, whatever the
> reason, will be handled. In this case, the interruption is always
> acknowledged.
>
> The following features will be added soon:
> - phb reset when switching to capi mode.
> - cxllib update to support new functions.
>
> Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com>
>
> Acked-by: Frederic Barrat <fbar...@linux.vnet.ibm.com>
>
> ---
> Changelog[v3]
> - Update commit message
>
> Changelog[v2]
> - Rebase to latest upstream.
> - Update the function is_page_fault()
> ---
> drivers/misc/cxl/cxl.h | 2 ++
> drivers/misc/cxl/fault.c | 15 ++-------------
> drivers/misc/cxl/pci.c | 47 ++++++++++++++++++++++++-----------------------
> 3 files changed, 28 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h
> index b1afecc..0167df8 100644
> --- a/drivers/misc/cxl/cxl.h
> +++ b/drivers/misc/cxl/cxl.h
> @@ -100,6 +100,8 @@ static const cxl_p1_reg_t CXL_XSL_FEC = {0x0158};
> static const cxl_p1_reg_t CXL_XSL_DSNCTL = {0x0168};
> /* PSL registers - CAIA 2 */
> static const cxl_p1_reg_t CXL_PSL9_CONTROL = {0x0020};
> +static const cxl_p1_reg_t CXL_XSL9_INV = {0x0110};
> +static const cxl_p1_reg_t CXL_XSL9_DEF = {0x0140};
> static const cxl_p1_reg_t CXL_XSL9_DSNCTL = {0x0168};
> static const cxl_p1_reg_t CXL_PSL9_FIR1 = {0x0300};
> static const cxl_p1_reg_t CXL_PSL9_FIR2 = {0x0308};
> diff --git a/drivers/misc/cxl/fault.c b/drivers/misc/cxl/fault.c
> index 6eed7d0..0cf7f4a 100644
> --- a/drivers/misc/cxl/fault.c
> +++ b/drivers/misc/cxl/fault.c
> @@ -204,22 +204,11 @@ static bool cxl_is_segment_miss(struct cxl_context
> *ctx, u64 dsisr)
>
> static bool cxl_is_page_fault(struct cxl_context *ctx, u64 dsisr)
> {
> - u64 crs; /* Translation Checkout Response Status */
> -
> if ((cxl_is_power8()) && (dsisr & CXL_PSL_DSISR_An_DM))
> return true;
>
> - if (cxl_is_power9()) {
> - crs = (dsisr & CXL_PSL9_DSISR_An_CO_MASK);
> - if ((crs == CXL_PSL9_DSISR_An_PF_SLR) ||
> - (crs == CXL_PSL9_DSISR_An_PF_RGC) ||
> - (crs == CXL_PSL9_DSISR_An_PF_RGP) ||
> - (crs == CXL_PSL9_DSISR_An_PF_HRH) ||
> - (crs == CXL_PSL9_DSISR_An_PF_STEG) ||
> - (crs == CXL_PSL9_DSISR_An_URTCH)) {
> - return true;
> - }
> - }
> + if (cxl_is_power9())
> + return true;
>
> return false;
> }
> diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
> index d18b3d9..a5baab3 100644
> --- a/drivers/misc/cxl/pci.c
> +++ b/drivers/misc/cxl/pci.c
> @@ -401,7 +401,8 @@ int cxl_calc_capp_routing(struct pci_dev *dev, u64
> *chipid,
> *capp_unit_id = get_capp_unit_id(np, *phb_index);
> of_node_put(np);
> if (!*capp_unit_id) {
> - pr_err("cxl: invalid capp unit id\n");
> + pr_err("cxl: invalid capp unit id (phb_index: %d)\n",
> + *phb_index);
> return -ENODEV;
> }
>
> @@ -475,37 +476,37 @@ static int init_implementation_adapter_regs_psl9(struct
> cxl *adapter,
> psl_fircntl |= 0x1ULL; /* ce_thresh */
> cxl_p1_write(adapter, CXL_PSL9_FIR_CNTL, psl_fircntl);
>
> - /* vccredits=0x1 pcklat=0x4 */
> - cxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0000000000001810ULL);
> -
> - /*
> - * For debugging with trace arrays.
> - * Configure RX trace 0 segmented mode.
> - * Configure CT trace 0 segmented mode.
> - * Configure LA0 trace 0 segmented mode.
> - * Configure LA1 trace 0 segmented mode.
> + /* Setup the PSL to transmit packets on the PCIe before the
> + * CAPP is enabled
> */
> - cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000000ULL);
> - cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000003ULL);
> - cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000005ULL);
> - cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000006ULL);
> + cxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0001001000002A10ULL);
>
> /*
> * A response to an ASB_Notify request is returned by the
> * system as an MMIO write to the address defined in
> - * the PSL_TNR_ADDR register
> + * the PSL_TNR_ADDR register.
> + * keep the Reset Value: 0x00020000E0000000
> */
> - /* PSL_TNR_ADDR */
>
> - /* NORST */
> - cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x8000000000000000ULL);
> + /* Enable XSL rty limit */
> + cxl_p1_write(adapter, CXL_XSL9_DEF, 0x51F8000000000005ULL);
> +
> + /* Change XSL_INV dummy read threshold */
> + cxl_p1_write(adapter, CXL_XSL9_INV, 0x0000040007FFC200ULL);
> +
> + if (phb_index == 3) {
> + /* disable machines 31-47 and 20-27 for DMA */
> + cxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE,
> 0x40000FF3FFFF0000ULL);
> + }
>
> - /* allocate the apc machines */
> - cxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000003FFFF0000ULL);
> + /* Snoop machines */
> + cxl_p1_write(adapter, CXL_PSL9_APCDEDALLOC, 0x800F000200000000ULL);
>
> - /* Disable vc dd1 fix */
> - if (cxl_is_power9_dd1())
> - cxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0400000000000001ULL);
> + if (cxl_is_power9_dd1()) {
> + /* Disabling deadlock counter CAR */
> + cxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0020000000000001ULL);
> + } else
> + cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x4000000000000000ULL);
>
> return 0;
> }
> --
> 2.7.4
>
LGTM
Reviewed-by: Vaibhav Jain <vaib...@linux.vnet.ibm.com>
