Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> writes: > On 11/02/2019 00:30, Benjamin Herrenschmidt wrote: > >> On Fri, 2019-02-08 at 14:51 +0000, Mark Cave-Ayland wrote: >>> >>> Indeed, but there are still some questions to be asked here: >>> >>> 1) Why were these bits removed from the original bitmask in the first place >>> without >>> it being documented in the commit message? >>> >>> 2) Is this the right fix? I'm told that MacOS guests already run without >>> this patch >>> on a G5 under 64-bit KVM-PR which may suggest that this is a workaround for >>> another >>> bug elsewhere in the 32-bit powerpc code. >>> >>> >>> If you think that these points don't matter, then I'm happy to resubmit the >>> patch >>> as-is based upon your comments above. >> >> We should write a test case to verify that FE0/FE1 are properly >> preserved/context-switched etc... I bet if we accidentally wiped them, >> we wouldn't notice 99.9% of the time. > > Right I guess it's more likely to cause in issue in the KVM PR case because > the guest > can alter the flags in a way that doesn't go through the normal process > switch mechanism. > > The original patchset at > https://www.mail-archive.com/linuxppc-dev@lists.ozlabs.org/msg98326.html does > include > some tests in the first few patches, but AFAICT they are concerned with the > contents > of the FP registers rather than the related MSRs.
fpu_preempt.c should be able to be adapted to also check the MSR bits. > Who is the right person to ask about fixing issues related to context > switching with > KVM PR? KVM PR doesn't really have a maintainer TBH. Feel like volunteering? :) > I did add the original author's email address to my first few emails but have > had no response back :/ Cyril who wrote the original FPU patch has moved on to other things. cheers
