On Wed, 7 Aug 2019, Christoph Hellwig wrote: > Mips uses the KSEG1 kernel memory segment to map dma coherent > allocations for non-coherent devices as uncacheable, and does not have > any kind of special support for DMA_ATTR_WRITE_COMBINE in the allocation > path. Thus supporting DMA_ATTR_WRITE_COMBINE in dma_mmap_attrs will > lead to multiple mappings with different caching attributes.
FYI, AFAIK _CACHE_UNCACHED_ACCELERATED (where supported) is effectively write-combine. Though IIUC someone would have to wire it in first. Maciej
