VSX vector paired instructions operates with octword (32-byte) operand for loads and stores between storage and a pair of two sequential Vector-Scalar Registers (VSRs). There are 4 word instructions and 2 prefixed instructions that provides this 32-byte storage access operations - lxvp, lxvpx, stxvp, stxvpx, plxvpx, pstxvpx.
Emulation infrastructure doesn't have support for these instructions, to operate with 32-byte storage access and to operate with 2 VSX registers. This patch series enables the instruction emulation support and adds test cases for them respectively. Changes in v2: ------------- * Fix suggestion from Sandipan, wrap ISA 3.1 instructions with cpu_has_feature(CPU_FTR_ARCH_31) check. * Rebase on latest powerpc next branch. Balamuruhan S (4): powerpc/sstep: support new VSX vector paired storage access instructions powerpc/sstep: support emulation for vsx vector paired storage access instructions powerpc ppc-opcode: add opcodes for vsx vector paired instructions powerpc sstep: add testcases for vsx load/store instructions arch/powerpc/include/asm/ppc-opcode.h | 11 ++ arch/powerpc/include/asm/sstep.h | 2 +- arch/powerpc/lib/sstep.c | 110 ++++++++++- arch/powerpc/lib/test_emulate_step.c | 273 ++++++++++++++++++++++++++ 4 files changed, 386 insertions(+), 10 deletions(-) base-commit: b2b46304e9360f3dda49c9d8ba4a1478b9eecf1d -- 2.24.1