On 5/20/22 7:11 PM, Nicholas Piggin wrote:
Excerpts from Paul E Murphy's message of May 21, 2022 12:21 am:
On 5/20/22 12:15 AM, Nicholas Piggin via Gcc wrote:
+PPC_FEATURE2_TAR
+ VSX facility is available.
Was manipulating the tar spr was once a privileged instruction, is this
a hint userspace can use the related instructions?
It can be disabled with facility control, and I guess there was
some consideration for how it might be used, e.g., "system software"
could use it for its own purpose then clear the bit for the application.
In practice I don't really know what makes use of this or whether
anything sanely can, it's marked reserved in the ABI. Would be
interesting to know whether there is much benefit to use it in the
compiler. The kernel could actually use it for something nifty if we
were able to prevent userspace from accessing it entirely...
It might be useful as a scratch register for indirect branches in some
odd cases, such as golang's preemptive userspace threading. Though, it
seems more trouble than its worth for a very limited benefit.
+
+PPC_FEATURE2_HAS_IEEE128
+ IEEE 128 is available? What instructions/data?
Maybe something like "IEEE 128 binary floating point instructions are
supported. Individual instruction availability is dependent on the
reported architecture version."?
Right, I just didn't know what architectural class of instructions
those are. Is it just VSX in general or are there some specific
things we can name?
I think ISA 3.1 buckets this into an OpenPOWER Linux Optional Feature
for "Quad-precision floating-point (QFP)". I guess ISA 3.0 predates
those categorizations.
+PPC_FEATURE2_MMA
+ MMA facility is available.
Maybe another note that specific instruction availability may depend on
the reported architecture version?
Yep. I wonder if it would help to note how these align (or don't) with
the various OpenPOWER features.
