On Tue, Jul 26, 2022 at 10:34 AM Pali Rohár <p...@kernel.org> wrote: > On Monday 25 July 2022 16:54:16 Segher Boessenkool wrote: > > On Mon, Jul 25, 2022 at 10:10:09PM +0200, Pali Rohár wrote: > > > On Monday 25 July 2022 16:20:49 Christophe Leroy wrote: > > > Now I did again clean test with same Debian 10 cross compiler. > > > > > > $ git clone > > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git && cd > > > linux > > > $ git checkout v5.15 > > > $ make mpc85xx_smp_defconfig ARCH=powerpc > > > CROSS_COMPILE=powerpc-linux-gnuspe- > > > $ make vmlinux ARCH=powerpc CROSS_COMPILE=powerpc-linux-gnuspe- > > > $ cp -a vmlinux vmlinux.v5.15 > > > $ git revert 9401f4e46cf6965e23738f70e149172344a01eef > > > $ make vmlinux ARCH=powerpc CROSS_COMPILE=powerpc-linux-gnuspe- > > > $ cp -a vmlinux vmlinux.revert > > > $ powerpc-linux-gnuspe-objdump -d vmlinux.revert > vmlinux.revert.dump > > > $ powerpc-linux-gnuspe-objdump -d vmlinux.v5.15 > vmlinux.v5.15.dump > > > $ diff -Naurp vmlinux.v5.15.dump vmlinux.revert.dump > > > > > > And there are: > > > > > > -c000c304: 7d 20 f8 29 lwarx r9,0,r31,1 > > > +c000c304: 7d 20 f8 28 lwarx r9,0,r31 > > > > > > I guess it must be reproducible this issue as I'm using regular > > > toolchain from distribution. > > > > > The EH field in larx insns is new since ISA 2.05, and some ISA 1.x cpu > > implementations actually raise an illegal insn exception on EH=1. It > > appears P2020 is one of those. > > > > P2020 has e500 cores. e500 cores uses ISA 2.03. So this may be reason. > But in official Freescale/NXP documentation for e500 is documented that > lwarx supports also eh=1. Maybe it is not really supported. > https://www.nxp.com/files-static/32bit/doc/ref_manual/EREF_RM.pdf (page 562) > At least there is NOTE: > Some older processors may treat EH=1 as an illegal instruction.
In commit d6ccb1f55ddf ("powerpc/85xx: Make sure lwarx hint isn't set on ppc32") this was clarified to affect (all?) e500v1/v2, this one apparently fixed it before, but Christophe's commit effectively reverted that change. I think only the simple_spinlock.h file actually uses EH=1 and this is not included in non-SMP kernels, so presumably the only affected machines were the rare dual-core e500v2 ones (p2020, MPC8572, bsc9132), which would explain why nobody noticed for the past 9 months. Arnd