Haren Myneni <ha...@linux.ibm.com> writes:
> DSI error will be generated when the paste operation is issued on
> the suspended NX window due to NX state changes. The hypervisor
Please spell out DSI and NX on the first usage.
> expects the partition to ignore this error during page pault
> handling. To differentiate DSI caused by an actual HW configuration
> or by the NX window, a new “ibm,pi-features” type value is defined.
> Byte 0, bit 3 of pi-attribute-specifier-type is now defined to
> indicate this DSI error. If this error is not ignored, the user
> space can get SIGBUS when the NX request is issued.
>
> This patch adds changes to read ibm,pi-features property and ignore
> DSI error in the page fault handling if CPU_FTR_NX_DSI if defined.
>
> Signed-off-by: Haren Myneni <ha...@linux.ibm.com>
> ---
> v2: Code cleanup as suggested by Christophe Leroy
>
> arch/powerpc/include/asm/cputable.h | 5 ++--
> arch/powerpc/kernel/prom.c | 36 +++++++++++++++++++++--------
> arch/powerpc/mm/fault.c | 17 +++++++++++++-
> 3 files changed, 45 insertions(+), 13 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/cputable.h
> b/arch/powerpc/include/asm/cputable.h
> index ae8c3e13cfce..8dc9949b6365 100644
> --- a/arch/powerpc/include/asm/cputable.h
> +++ b/arch/powerpc/include/asm/cputable.h
> @@ -192,6 +192,7 @@ static inline void cpu_feature_keys_init(void) { }
> #define CPU_FTR_P9_RADIX_PREFETCH_BUG
> LONG_ASM_CONST(0x0002000000000000)
> #define CPU_FTR_ARCH_31
> LONG_ASM_CONST(0x0004000000000000)
> #define CPU_FTR_DAWR1
> LONG_ASM_CONST(0x0008000000000000)
> +#define CPU_FTR_NX_DSI
> LONG_ASM_CONST(0x0010000000000000)
Can we make this an MMU feature?
We have a lot more free MMU feature bits, it should just be a case of
s/cpu/mmu/ pretty much everywhere you use it.
> #ifndef __ASSEMBLY__
>
> @@ -429,7 +430,7 @@ static inline void cpu_feature_keys_init(void) { }
> CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
> CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
> CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_P9_TLBIE_STQ_BUG | \
> - CPU_FTR_P9_TLBIE_ERAT_BUG | CPU_FTR_P9_TIDR)
> + CPU_FTR_P9_TLBIE_ERAT_BUG | CPU_FTR_P9_TIDR | CPU_FTR_NX_DSI)
> #define CPU_FTRS_POWER9_DD2_0 (CPU_FTRS_POWER9 |
> CPU_FTR_P9_RADIX_PREFETCH_BUG)
> #define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | \
> CPU_FTR_P9_RADIX_PREFETCH_BUG | \
> @@ -451,7 +452,7 @@ static inline void cpu_feature_keys_init(void) { }
> CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
> CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
> CPU_FTR_ARCH_300 | CPU_FTR_ARCH_31 | \
> - CPU_FTR_DAWR | CPU_FTR_DAWR1)
> + CPU_FTR_DAWR | CPU_FTR_DAWR1 | CPU_FTR_NX_DSI)
You're turning that bit on by default for Power9 and Power10 - is that
correct?
If so do you have a documentation source for that?
cheers
