On Wed May 10, 2023 at 1:31 PM AEST, Rohan McLure wrote: > The idle_state entry in the PACA on PowerNV features a bit which is > atomically tested and set through ldarx/stdcx. to be used as a spinlock. > This lock then guards access to other bit fields of idle_state. KCSAN > cannot differentiate between any of these bitfield accesses as they all > are implemented by 8-byte store/load instructions, thus cores contending > on the bit-lock appear to data race with modifications to idle_state. > > Separate the bit-lock entry from the data guarded by the lock to avoid > the possibility of data races being detected by KCSAN. > > Suggested-by: Nicholas Piggin <npig...@gmail.com> > Signed-off-by: Rohan McLure <rmcl...@linux.ibm.com>
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
