[PATCH] ASoC: fsl_xcvr: Enable 2 * TX bit clock for spdif only case

[Shengjiu Wang]

The bit 10 in TX_DPTH_CTRL register controls the TX clock rate.
If this bit is set, TX datapath clock should be = 2* TX bit rate.
If this bit is not set, TX datapath clock should be 10* TX bit rate.

As the spdif only case, we always use 2 * TX bit clock, so
this bit need to be set.

Signed-off-by: Shengjiu Wang <shengjiu.w...@nxp.com>
---
 sound/soc/fsl/fsl_xcvr.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/sound/soc/fsl/fsl_xcvr.c b/sound/soc/fsl/fsl_xcvr.c
index fa0a15263c66..77f8e2394bf9 100644
--- a/sound/soc/fsl/fsl_xcvr.c
+++ b/sound/soc/fsl/fsl_xcvr.c
@@ -414,6 +414,16 @@ static int fsl_xcvr_prepare(struct snd_pcm_substream 
*substream,
 
        switch (xcvr->mode) {
        case FSL_XCVR_MODE_SPDIF:
+               if (xcvr->soc_data->spdif_only && tx) {
+                       ret = regmap_update_bits(xcvr->regmap, 
FSL_XCVR_TX_DPTH_CTRL_SET,
+                                                
FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM,
+                                                
FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM);
+                       if (ret < 0) {
+                               dev_err(dai->dev, "Failed to set bypass fem: 
%d\n", ret);
+                               return ret;
+                       }
+               }
+               fallthrough;
        case FSL_XCVR_MODE_ARC:
                if (tx) {
                        ret = fsl_xcvr_en_aud_pll(xcvr, fout);
-- 
2.34.1