On 2024-03-25 16:34, Nathan Lynch wrote:
Mathieu Desnoyers <mathieu.desnoy...@efficios.com> writes:
In the powerpc architecture support within the liburcu project [1]
we have a cache line size defined as 256 bytes with the following
comment:
/* Include size of POWER5+ L3 cache lines: 256 bytes */
#define CAA_CACHE_LINE_SIZE 256
I recently received a pull request on github [2] asking to
change this to 128 bytes. All the material provided supports
that the cache line sizes on powerpc are 128 bytes or less (even
L3 on POWER7, POWER8, and POWER9) [3].
I wonder where the 256 bytes L3 cache line size for POWER5+
we have in liburcu comes from, and I wonder if it's the right choice
for a cache line size on all powerpc, considering that the Linux
kernel cache line size appear to use 128 bytes on recent Power
architectures. I recall some benchmark experiments Paul and I did
on a 64-core 1.9GHz POWER5+ machine that benefited from a 256 bytes
cache line size, and I suppose this is why we came up with this
value, but I don't have the detailed specs of that machine.
Any feedback on this matter would be appreciated.
For what it's worth, I found a copy of an IBM Journal of Research &
Development article confirming that POWER5's L3 had a 256-byte line
size:
Each slice [of the L3] is 12-way set-associative, with 4,096
congruence classes of 256-byte lines managed as two 128-byte sectors
to match the L2 line size.
https://www.eecg.utoronto.ca/~moshovos/ACA08/readings/power5.pdf
I don't know of any reason to prefer 256 over 128 for current Power
processors though.
Thanks for the pointer. I will add a reference to it in the liburcu
source code to explain the cache line size choice.
Mathieu
--
Mathieu Desnoyers
EfficiOS Inc.
https://www.efficios.com
