On 2/3/26 3:44 PM, Lukas Wunner wrote:
On Wed, Jan 28, 2026 at 08:45:36PM +0800, Shuai Xue wrote:
The revised the commit message is:
PCI/AER: Only clear error bits in PCIe Device Status register
Currently, pcie_clear_device_status() clears the entire PCIe Device
Status register (PCI_EXP_DEVSTA), which includes both error status bits
and other status bits.
According to PCIe Base Spec r6.0 sec 7.5.3.5, the Device Status register
contains different types of status bits:
Always cite the latest spec revision, i.e. PCIe r7.0 sec 7.5.3.5.
Sure, I will update the cite version.
- RW1C (read/write 1 to clear) non-error bits: For example, Emergency
Power Reduction Detected (bit 6). Unconditionally clearing these bits
can interfere with other drivers or subsystems that rely on them.
It would be good to explicitly call out that this bit was introduced with
PCIe r5.0 in 2019 and that it's currently the only writable bit in the
register besides the error bits.
Sure, will add it.
- Reserved bits: May be used for future features and should be preserved.
Wrong, they're marked "RsvdZ" (not "RsvdP"), so they're supposed to be
written as zero (not preserved).
Thanks for correcting me. Will fix it.
Thanks,
Lukas
Thanks for valuable comments.
Shuai
