On 5/20/26 00:49, Manivannan Sadhasivam wrote:
On Wed, May 20, 2026 at 12:27:21AM +0800, Hans Zhang wrote:
On 5/20/26 00:15, Manivannan Sadhasivam wrote:
On Wed, May 20, 2026 at 12:09:28AM +0800, Hans Zhang wrote:
On 5/19/26 21:57, Manivannan Sadhasivam wrote:
On Sat, May 09, 2026 at 09:51:49PM +0800, Hans Zhang wrote:
The DWC PCIe core and its many platform drivers repeatedly call
dw_pcie_find_capability(pci, PCI_CAP_ID_EXP) to obtain the offset of the
PCI Express Capability structure. This is wasteful and makes the code
verbose. And some even search for the PCI_CAP_ID_EXP offset value within
the suspend/resume functions.
Sashiko has flagged some real issues with this series in accessing DBI space
very early and 'pci->pcie_cap' being 0.
Hi Mani,
We have discussed this issue in the Cadence driver. I think it won't cause
any problems. Specifically as follows:
https://lore.kernel.org/linux-pci/[email protected]/
"""
As per PCIe r7.0, sec 7.5.1.1.11, Since all PCI Express Functions are
required to implement the PCI Express Capability structure, which
must be included somewhere in this linked list.
"""
Bjorn also responded as follows:
https://lore.kernel.org/linux-pci/20260505212306.GA744158@bhelgaas/
"""
It's true that all Root Ports must have a PCIe Capability.
"""
Ok, what about reading the DBI registers very early?
Hi Mani,
Yes. I have performed the DBI read register operation at the very beginning
of the following code.
dw_pcie_ep_init()
dw_pcie_get_pcie_cap(pci);
dw_pcie_host_init
dw_pcie_get_pcie_cap(pci);
These both calls will cause crash on a lot of platforms because these will be
reading the DBI registers while the resources are not enabled.
Hi Mani,
Next, I will check all the DBI register-related issues. It will be fixed
in the next version. Thank you very much.
Best regards,
Hans
