Bjorn suggests "the PCI core should do pci_enable_pcie_error_reporting() independent of whether the device has an AER Capability":
https://lore.kernel.org/r/20260826212619.GA1566339@bhelgaas/ This is done in patch [7/7]. The preceding patches contain prep work. For context, PCIe r7.1 sec 6.2.1 defines two error reporting paradigms: AER and baseline capability. The latter relies (solely) on the error enable/status bits in the Device Control and Device Status registers, which exist on every PCIe device. The kernel has supported the AER paradigm for 20 years. With the present series, it gains support for the baseline capability paradigm. Patches [1/7] and [2/7] reinstate DPC on AER-incapable Downstream Ports. The kernel used to support this until 2020. It is hereby fixed because it eases introduction of baseline capability error reporting in the subsequent patches. Lukas Wunner (6): PCI/DPC: Avoid access to non-existent AER capability PCI/DPC: Reinstate support for AER-incapable ports PCI/AER: Drop AER native check from handles_cxl_errors() PCI/AER: Move AER capability check out of pcie_aer_is_native() PCI/AER: Renumber severity constants PCI/AER: Enable baseline capability error reporting Yury Murashka (1): PCI/ERR: Avoid stale error status bits on recovery failure .../ABI/testing/sysfs-bus-pci-devices-aer | 26 +++++++--- Documentation/PCI/pcieaer-howto.rst | 9 ++-- drivers/pci/pcie/aer.c | 51 +++++++++++-------- drivers/pci/pcie/aer_cxl_rch.c | 3 +- drivers/pci/pcie/dpc.c | 24 ++++----- drivers/pci/pcie/err.c | 5 ++ include/linux/aer.h | 8 +-- include/ras/ras_event.h | 2 +- 8 files changed, 72 insertions(+), 56 deletions(-) -- 2.53.0
