Hello all, On Wed, Jun 17, 2009 at 2:37 AM, FUJITA Tomonori<[email protected]> wrote: > On Wed, 17 Jun 2009 10:18:45 +1000 > Benjamin Herrenschmidt <[email protected]> wrote: > >> On Tue, 2009-06-16 at 20:02 +0200, Arnd Bergmann wrote: >> > On Tuesday 16 June 2009, Scott Wood wrote: >> > > > If the >> > > > device is the only one, you can also use dma_alloc_noncoherent() and >> > > > flush explicitly with dma_cache_sync(). >> > > >> > > I don't see how that would help -- aren't those also controlled by >> > > CONFIG_NOT_COHERENT_CACHE? >> > >> > Ah, yes you are right. PowerPC implements dma_alloc_noncoherent as >> > dma_alloc_coherent, so dma_cache_sync() is actually a NOP (or should be). >> >> But we still need to sync the result of dma_map_* when used multiple >> times for a single mapping. > > We have dma_sync_{single|sg}_for_{cpu|device} API for the above > purpose. > > dma_cache_sync is supposed to be used only with the buffers that > dma_alloc_noncoherent() returns. On architecutures that maps > dma_alloc_noncoherent to dma_alloc_coherent, dma_cache_sync() is > supposed to be NOP.
This discussion raised some doubt with me about my use case: I my case (note I am not the poster) I am using (what LDD3 calls) streaming mappings: I use pci_map_sg(), have the device perform either DMA master reads or writes to the bus address using PCIe. After that, I use pci_unmap_sg(). My assumption is that pci_unmap_sg() either makes the cache coherent or invalidated and thus I do not need to take further actions. This is on a MPC83xx or 85xx system. Is this assumption correct? Regards, Leon/ -- Leon _______________________________________________ Linuxppc-dev mailing list [email protected] https://lists.ozlabs.org/listinfo/linuxppc-dev
