On Jun 26, 2012, at 5:25 AM, Zhao Chenhui wrote: > Do hardware timebase sync. Firstly, stop all timebases, and transfer > the timebase value of the boot core to the other core. Finally, > start all timebases. > > Only apply to dual-core chips, such as MPC8572, P2020, etc. > > Signed-off-by: Zhao Chenhui <chenhui.z...@freescale.com> > Signed-off-by: Li Yang <le...@freescale.com> > --- > Changes for v6: > * added 85xx_TB_SYNC > * added isync() after set_tb() > * removed extra entries from mpc85xx_smp_guts_ids
Why only on dual-core chips? Is this because of something related to 2 cores, or related to corenet vs non-corenet SoCs and how turning on/off the timebase works in the SOC? - k _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
