On Wed, Apr 03, 2013 at 09:09:11PM +0800, Zhao Chenhui wrote: > These cache operations support Freescale SoCs based on BOOK3E. > Move L1 cache operations to fsl_booke_cache.S in order to maintain > easily. And, add cache operations for backside L2 cache and platform cache. > > The backside L2 cache appears on e500mc and e5500 core. The platform cache > supported by this patch is L2 Look-Aside Cache, which appears on SoCs > with e500v1/e500v2 core, such as MPC8572, P1020, etc. > > Signed-off-by: Zhao Chenhui <chenhui.z...@freescale.com> > Signed-off-by: Li Yang <le...@freescale.com> > --- > arch/powerpc/include/asm/cacheflush.h | 8 ++ > arch/powerpc/kernel/Makefile | 1 + > arch/powerpc/kernel/fsl_booke_cache.S | 210 > +++++++++++++++++++++++++++++++++ > arch/powerpc/kernel/head_fsl_booke.S | 74 ------------ > 4 files changed, 219 insertions(+), 74 deletions(-) > create mode 100644 arch/powerpc/kernel/fsl_booke_cache.S
Are there any comments about the set of patches? -Chenhui _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev