Hi Michael,
On Fri, Jan 31, 2014 at 03:18:30PM -0800, David Hawkins wrote:
1. Peripheral board DMA (board-to-board)
2. Peripheral board DMA to host memory.
3. Host (root complex) DMA.
As far as "verification" of your custom peripheral board FPGA IP is
concerned, if I was a customer, and you had data for (1) and (2),
I'd be pretty happy (and could care less about (2), since its so
system dependent).
Usually I would totally agree with you and try to implement the benchmark
using DMA transfers Unfortunately, we have some boards and IP cores that
do not support DMA transfers, or the target system must not do by a
requirement, and as I have no influence on these, I had to investigate
on how to improve my throughput.
Ah, I see, that does make your life difficult then.
I've submitted a RFC Patch earlier today, which allowed me to perform
PCIe read bursts on IO memory, achieving 18 MB/s instead of the 3 MB/s
I got when using non-cached reads. However, I had to ioremap() my
memory, like Gabriel said, using write-thru configuration.
That sounds like a reasonable compromise.
Cheers,
Dave
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