On Feb 28, 2014, at 2:48 AM, Zhao Qiang <b45...@freescale.com> wrote:
> There is QE on platform T104x, add support. > Call funcs qe_ic_init and qe_init if CONFIG_QUICC_ENGINE is defined. > > Signed-off-by: Zhao Qiang <b45...@freescale.com> > --- > arch/powerpc/platforms/85xx/corenet_generic.c | 32 +++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) Can you use mpc85xx_qe_init() instead? > > diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c > b/arch/powerpc/platforms/85xx/corenet_generic.c > index fbd871e..f8c8e0c 100644 > --- a/arch/powerpc/platforms/85xx/corenet_generic.c > +++ b/arch/powerpc/platforms/85xx/corenet_generic.c > @@ -26,6 +26,8 @@ > #include <asm/udbg.h> > #include <asm/mpic.h> > #include <asm/ehv_pic.h> > +#include <asm/qe.h> > +#include <asm/qe_ic.h> > > #include <linux/of_platform.h> > #include <sysdev/fsl_soc.h> > @@ -38,6 +40,10 @@ void __init corenet_gen_pic_init(void) > unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU | > MPIC_NO_RESET; > > +#ifdef CONFIG_QUICC_ENGINE > + struct device_node *np; > +#endif > + > if (ppc_md.get_irq == mpic_get_coreint_irq) > flags |= MPIC_ENABLE_COREINT; > > @@ -45,6 +51,16 @@ void __init corenet_gen_pic_init(void) > BUG_ON(mpic == NULL); > > mpic_init(mpic); > + > +#ifdef CONFIG_QUICC_ENGINE > + np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); > + if (np) { > + qe_ic_init(np, 0, qe_ic_cascade_low_mpic, > + qe_ic_cascade_high_mpic); > + of_node_put(np); > + } > +#endif > + > } > > /* > @@ -52,11 +68,24 @@ void __init corenet_gen_pic_init(void) > */ > void __init corenet_gen_setup_arch(void) > { > +#ifdef CONFIG_QUICC_ENGINE > + struct device_node *np; > +#endif > mpc85xx_smp_init(); > > swiotlb_detect_4g(); > > pr_info("%s board from Freescale Semiconductor\n", ppc_md.name); > + > +#ifdef CONFIG_QUICC_ENGINE > + np = of_find_compatible_node(NULL, NULL, "fsl,qe"); > + if (!np) { > + pr_err("%s: Could not find Quicc Engine node\n", __func__); > + return; This doesn’t seem like an reasonable error message for common corenet platform. It seems reasonable to build QE support but boot on a chip w/o QE. > + } > + qe_reset(); > + of_node_put(np); > +#endif > } > > static const struct of_device_id of_device_ids[] = { > @@ -81,6 +110,9 @@ static const struct of_device_id of_device_ids[] = { > { > .compatible = "fsl,qoriq-pcie-v3.0", > }, > + { > + .compatible = "fsl,qe", > + }, > /* The following two are for the Freescale hypervisor */ > { > .name = "hypervisor", > -- > 1.8.5 > > > _______________________________________________ > Linuxppc-dev mailing list > Linuxppc-dev@lists.ozlabs.org > https://lists.ozlabs.org/listinfo/linuxppc-dev _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev