Hello All I am debugging a UART issue on a Freescale PowerPC SOC.
My observations are: When FiFo mode is enabled FCR[FEN]=1, and the Fifo size is 16byte. I see console prints not coming properly, lot of missing characters. But here when I change the tx_loadsz to 8, the UART works fine. [PORT_16550A] = { .name = "16550A", .fifo_size = 16, - .tx_loadsz = 16, + .tx_loadsz = 8, .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, .flags = UART_CAP_FIFO, }, Can anybody help to understand what is the significance of tx_loadsz. From the code (drivers/serial/tty/8250/8250.c), looks like this parameter controls the bytes we write to the UART Tx register at one time. So ideally this should be equal to the Fifo size. I also see certain UARTs where tx_loadsz is not equal to fifo_size, less than fifo_size. Please help me to understand how should tx_loadsz be determined? Many Thanks Poonam
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