On Mon, 2014-03-03 at 17:50 +0800, Shengzhou Liu wrote:
> + corenet-cf@18000 {
> + compatible = "fsl,corenet-cf";
> + reg = <0x18000 0x1000>;
> + interrupts = <16 2 1 31>;
> + fsl,ccf-num-csdids = <32>;
> + fsl,ccf-num-snoopids = <32>;
> + };
This is not compatible with "fsl,corenet-cf".
> + clockgen: global-utilities@e1000 {
> + compatible = "fsl,t2080-clockgen", "fsl,qoriq-clockgen-2.0";
> + reg = <0xe1000 0x1000>;
> + };
See Documentation/devicetree/bindings/clock/corenet-clock.txt
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /*
> + * Temporarily add next-level-cache info in each cpu node so
> + * that uboot can do L2 cache fixup. This can be removed once
> + * u-boot can create cpu node with cache info.
> + */
Is there a reason why this is temporary? What do we gain from U-Boot
doing the fixup? Is U-Boot doing the rest of the fixup (adding ePAPR
properties to the L2 cache nodes)?
-Scott
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