On 10/09/2014 05:18 PM, Anshuman Khandual wrote: > This patch enables support for hardware instruction breakpoints > on POWER8 with the help of a new register CIABR (Completed > Instruction Address Breakpoint Register). With this patch, single > hardware instruction breakpoint can be added and cleared during > any active xmon debug session. This hardware based instruction > breakpoint mechanism works correctly along with the existing TRAP > based instruction breakpoints available on xmon.
Hey Michael, Any updates on this patch ? _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
