On Fri, Aug 28, 2015 at 05:39:21PM +0200, Peter Zijlstra wrote: > On Fri, Aug 28, 2015 at 10:16:02PM +0800, Boqun Feng wrote: <snip> > > > > Ah.. just read through the thread you mentioned, I might misunderstand > > you, probably because I didn't understand RCpc well.. > > > > You are saying that in a RELEASE we -might- switch from smp_lwsync() to > > smp_mb() semantically, right? I guess this means we -might- switch from > > RCpc to RCsc, right? > > > > If so, I think I'd better to wait until we have a conclusion for this. > > Yes, the difference between RCpc and RCsc is in the meaning of RELEASE + > ACQUIRE. With RCsc that implies a full memory barrier, with RCpc it does > not. > > Currently PowerPC is the only arch that (can, and) does RCpc and gives a > weaker RELEASE + ACQUIRE. Only the CPU who did the ACQUIRE is guaranteed > to see the stores of the CPU which did the RELEASE in order. > > As it stands, RCU is the only _known_ codebase where this matters, but > we did in fact write code for a fair number of years 'assuming' RELEASE > + ACQUIRE was a full barrier, so who knows what else is out there. > > > RCsc - release consistency sequential consistency > RCpc - release consistency processor consistency > > https://en.wikipedia.org/wiki/Processor_consistency (where they have > s/sequential/causal/)
Thank you for your detailed explanation! Much clear now ;-) Regards, Boqun
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