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Actually, we figured out what was going on. Apparently we
left one of the interrupt lines disconnected from the CPU in the FPGA design.
Thanks for all the help guys, I really do appreciate it. Clint Thomas From: Clint Thomas Sent: Friday, September 01, 2006 6:58 PM To: [email protected] Cc: 'Peter Ryser '; Jason Lamb Subject: RE: PPC405 system slow boot The xparameters.h file is generated by the Xilinx EDK
for our FPGA, so I don't see how there could be a mismatch. Using Chipscope, we
were able to find that the interrupt controller is triggered on kernel
initialization, but after the kernel has finished loading, the system moves to a
snail's pace at login.
Does Linux use a different set of code to handle the
UART, INTC, etc. after the kernel is loaded? The system appears to work
perfectly up until after the kernel is done loading. From: Peter Ryser [mailto:[EMAIL PROTECTED] Sent: Monday, August 28, 2006 8:45 PM To: Clint Thomas Cc: [email protected] Subject: Re: PPC405 system slow boot check the interrupt sub-system of your design. What you describe typically happens when the PPC does not get any interrupts from the UART. It's most likely a mismatch between your hardware and the xparameters.h. - Peter Clint Thomas wrote:
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