Hi all may be not really related to linux but I hope some body can help me with this
As you know PPC405 runs the instruction at 0xfffffffc address as it's first instruction when generating a base system for ML403 using XPS, one should certainly add PLB BRAM controller , this module will reside on PLB and contains some BRAM instances. A Code called boot loop is located in these block memories. PPC405 runs boot loop until sysace makes linux elf ready. Looking in the generated xparameters.h you see that the base address for PLB BRAM IF is 0xffff0000 and since the first instruction should be located at 0xfffffffc , you have to define the size of this PLB BRAM IF equal to 64k when generating your system in XPS. Now looking at ultracontroller reference design one can see that PPC405 looks for 0xfffffffc address on its IS OCM bus , but in regular designs as you see PPC405 looks for this address on PLB Instruction bus, I'm wondering how PPC understands to do so in each of these designs? Does PPC have a special input port which is assigned a fix value and indicates where should PPC look for 0xfffffffc address ( ISOCM or IS PLB )? thanks. _________________________________________________________________ Connect to the next generation of MSN Messenger http://imagine-msn.com/messenger/launch80/default.aspx?locale=en-us&source=wlmailtagline _______________________________________________ Linuxppc-embedded mailing list [email protected] https://ozlabs.org/mailman/listinfo/linuxppc-embedded
