Hi, the MPC8360 has two DDR SDRAM controllers. In the 2x32 bit mode data transfers from/to the SDRAM can be handled by the MPC and the QUICC Engine independently. For instance, the core can access one bank and the QUICC Engine can access the other bank via DMA for lookup tables, temporary buffers, etc. in the same time.
IMHO the Linux Kernel supports only one linear virtual address space. So how could the kernel memory management (DMA, alloc, etc.) ensure, that data transfers go from/to the QUICC Engine to/from the second SDRAM bank? Does anybody know if bank-separated memory management is supported by the Linux Kernel, especially for the MPC8360? Thanks in advance Jens _______________________________________________ Linuxppc-embedded mailing list [email protected] https://ozlabs.org/mailman/listinfo/linuxppc-embedded
