On 3/14/14, 10:29 AM, "Miroslav Lichvar" <[email protected]> wrote:

>On Fri, Mar 14, 2014 at 04:59:41PM +0000, Vick, Matthew wrote:
>> One thing we could look at is adding a write flush to the drivers after
>> writing their registers (for example, the SYSTIM registers on i210) to
>> force the writes through quicker, but on a quiet network I wouldn't
>>expect
>> to see a massive improvement. Would you like me to get a patch together
>> for you to try out on i210 and see if it improves the initial jump?
>
>Hm, the reading delay observed by the PTP_SYS_OFFSET ioctl is around
>4900 ns with the i210, which is almost all of the error. Is it
>possible that writing to the register is already much faster than
>reading? So it would not help much even if writing had zero delay.

Reading a PCIe register is tricky, since it has to flush any posted
transactions (meaning all PCIe writes have to complete), send the read
request, and then actually get the result. It's also important to note
that reading the clock on i210 is 3 PCIe reads.

Writes are "faster" in the sense that there is no completion from the
device, but "slower" in the sense that writes can theoretically happen
whenever there's time for it instead of being an immediate request. A
write flush would force the writes to happen more quickly, so the clock
gets the change slightly faster, but if all of the latency is in reading
the registers so we know what to adjust, I wouldn't expect to get any
meaningful boost from a write flush. It's just the PCIe latency we have to
accept at that point.

Cheers,
Matthew


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