From: Vincent Cheng <vincent.cheng...@renesas.com>
When clock stepping is unable to happen instantaneously the subsequent
timestamps after a clock step does not reflect the step result and
undesired clock freq and clock steps would occur.
When using ts2phc to synchronize timestamping clock using external
1 PPS, it could take up to 1 second for the timestamps to reflect the
clock step.
step_window, when set, indicates the number of Sync events after
a clock step in which the clock servo will not do any frequency or
step adjustments.
Below example illustrates the problem for 16 PPS when clock step
does not occur before the next set of timestamps are received.
Debug statements were added to show T1 and T2 timestamps and the freq
and step requests at clock_sychronize() for SERVO_JUMP.
ptp4l[255352.651]: selected best master clock 00b0ae.fffe.02e810
ptp4l[255352.651]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE
ptp4l[255352.717]: debug: T1: 1611934788908411436 T2: 10341336582
...
ptp4l[255352.904]: master offset -1611934778567080326 s0 freq -128 path
delay 5436
ptp4l[255352.967]: debug: T1: 1611934789158411436 T2: 10591336566
ptp4l[255352.967]: debug: adj freq -159.999967232
ptp4l[255352.971]: debug: step 1611934778567080308
...
ptp4l[255353.217]: debug: T1: 1611934789408411436 T2: 10841336502
ptp4l[255353.217]: debug: adj freq 0.000027648
ptp4l[255353.221]: debug: step 1611934778567080368
At 16 PPS, the packet interval is 0.0625 seconds.
The first step occurs at [255352.971], T2 is around 10 seconds.
The next step occurs at [255353.221], T2 is still around 10 seconds.
In an ideal setup, the clock step would be reflected instantaneously
and the correct T2 should be around 1611934799 seconds.
Below shows result of adding step_window.
Clock step occurs at s1, SERVO_JUMP. s2 is SERVO_LOCKED.
The setup is using ts2phc to synhronize the network PHC to external time
stamp signal. The progation delay of the 1 PPS signals have a worst case
of 2 seconds.
step_window is set to 0 (default 0), so retains original behavior,
ie. will use subsequent timestamps to calculate next clock adjustments.
logSyncInterval -4
logMinDelayReqInterval -4
first_step_threshold 0.001000000
step_threshold 0.000001000
step_window 0
ptp4l[3831.568]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE
ptp4l[3831.634]: master offset -1613279867776376096 s0 freq +0 path delay
7711
ptp4l[3831.698]: master offset -1613279867776376100 s1 freq -64 path delay
7707
ptp4l[3831.822]: master offset -1613279867776376124 s0 freq -64 path delay
7711
ptp4l[3831.884]: master offset -1613279867776376140 s0 freq -64 path delay
7711
ptp4l[3831.948]: master offset -1613279867776376124 s1 freq +192 path delay
7703
...
ptp4l[3832.447]: master offset -1613279867776376180 s0 freq -128 path delay
7707
ptp4l[3832.511]: master offset -1613279867776376166 s1 freq +96 path delay
7705
ptp4l[3833.572]: rms 5875888855636859904 max 6453119470999989248 freq +67785
+/- 119252 delay 8448 +/- 2020
ptp4l[3834.634]: rms 6453119470999931904 max 6453119470999931904 freq -139
+/- 360 delay 7711 +/- 21
ptp4l[3835.697]: rms 7237815975126660096 max 8136258558135193600 freq +75045
+/- 113951 delay -137763073020509120 +/- 496711823640969536
ptp4l[3836.696]: rms 6068654064854322176 max 8136258558135192576 freq +69808
+/- 117623 delay 8492 +/- 1500
ptp4l[3837.759]: rms 2174226957844811520 max 2174226957844814848 freq -3409
+/- 6863 delay 7697 +/- 43
ptp4l[3838.821]: rms 1348149014385676288 max 2174226957844810752 freq -85
+/- 39 delay -113134119417210480 +/- 265323028344133024
ptp4l[3839.821]: rms 703483405420974336 max 703483405420974336 freq -199 +/-
52 delay 7712 +/- 11
The multiple clock steps (s1 - [3831.698], [3831.948], etc.) overlap each other
and causes convergence propblems for higher packet rates like 16 packets per
second.
Setting step_window to 32 (2 seconds at 16 PPS):
logSyncInterval -4
logMinDelayReqInterval -4
first_step_threshold 0.001000000
step_threshold 0.000001000
step_window 32
ptp4l[4051.547]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE
ptp4l[4051.676]: master offset -1613280090261264012 s0 freq +0 path delay
7723
ptp4l[4051.740]: master offset -1613280090261263998 s1 freq +224 path delay
7701
ptp4l[4051.926]: master offset -1613280090261264042 s0 freq -256 path delay
7709
ptp4l[4052.051]: master offset -261264088 s0 freq +1000000000 path delay
7727
ptp4l[4052.176]: master offset -261264116 s0 freq -384 path delay 7703
..
ptp4l[4053.551]: master offset -261264516 s0 freq -192 path delay 7699
ptp4l[4053.676]: master offset -261264558 s0 freq -192 path delay 7717
ptp4l[4053.801]: master offset -598 s2 freq -374 path delay 7721
ptp4l[4053.802]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED
ptp4l[4053.864]: master offset -580 s2 freq -535 path delay 7703
ptp4l[4053.926]: master offset -538 s2 freq -667 path delay 7689
ptp4l[4053.989]: master offset -506 s2 freq -797 path delay 7689
ptp4l[4054.051]: master offset -444 s2 freq -887 path delay 7695
ptp4l[4054.114]: master offset -420 s2 freq -996 path delay 7695
ptp4l[4054.176]: master offset -332 s2 freq -1034 path delay 7687
ptp4l[4054.239]: master offset -276 s2 freq -1077 path delay 7691
ptp4l[4054.301]: master offset -224 s2 freq -1108 path delay 7695
ptp4l[4054.364]: master offset -146 s2 freq -1097 path delay 7681
ptp4l[4054.426]: master offset -114 s2 freq -1109 path delay 7681
ptp4l[4054.489]: master offset -34 s2 freq -1063 path delay 7705
ptp4l[4054.551]: master offset 2 s2 freq -1038 path delay 7705
The first clock step at[4051.740] is given a chance to complete. After
2 seconds (ie. 32 Sync packets at 16 PPS rate), the master offset at [4053.801]
properly reflects the results of the first clock step.
v2:
Suggested by: Richard Cochran <richardcoch...@gmail.com>
- Avoid using a timer with asynchronous signal.
- Use step_window in terms of number of Sync events to skip.
- Simplifies implementation to a simple counter.
Vincent Cheng (1):
clock: Introduce step_window to free run x Sync events after a clock
step.
clock.c | 17 +++++++++++++++++
config.c | 1 +
ptp4l.8 | 8 ++++++++
3 files changed, 26 insertions(+)
--
2.7.4
_______________________________________________
Linuxptp-devel mailing list
Linuxptp-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/linuxptp-devel
