On Tue, 22 Nov 2016 11:00:12 -0800, Richard Cochran wrote:
> PS IIRC, there is a technical hurdle to achieve real PHY time stamps
> in gigabit devices. Are you sure the Atheros time stamps in the PHY
> and not on the MII bus inputs/outputs? (Just curious)
I'm not sure I'm qualified to answer that question, but I'm including
the relevant figures and text excerpts that I found in the ar8031
datasheet below in case that helps.
Top Level Use of AR8031 in an IEEE 1588v2 system:
+-----------------+ +-------------+
| AR8031 | RGMII/ | Controller |
| +-------------+ | SGMII |-----+ |
Line | |1588v2 Module| |<-------->| | |
side | | +-----+ | | | MAC | |
<--->| | | RTC | | | | | |
| | +-----+ | |<-------->| | |
| +-------------+ | SMI |-----+ |
+-----------------+ +-------------+
A A |
| | V
1588 ref. Local PPS
clock 25MHz
(optional)
Top Level Diagram of the AR8031's IEEE 1588v2 module:
+---------------------------+
| 1588v2 Module |
Time of Day | +---------------------+ |
<--------------+--| IEEE 1588 Real | |
| | Time Clock | |
<--------------+--| | |
PPS | +---------------------+ |
| A |
| | |
| V |
MDC/MDIO | +---------------------+ |
<--------------+->| IEEE 1588 Control | |
| +---------------------+ |
| A |
| | |
| V |
| +---------------------+ |
RGMII/SGMII | | IEEE 1588 Timestamp | |
<--------------+->|Unit Packet Detection| |
| | and Processing | |
| +---------------------+ |
+---------------------------+
Block Diagram of the AR8031 1588v2 module:
Rx Tx
A | RGMII/SGMII
| |<------------->
| +++
| | | Tx FIFO
| +++
| |
| V
+----------+-----+
| . | | +-------------+
| . '-----+------->| |
| ..............|<-------| |
| miiswitch | | IEEE 1588v2 |
| ..............|------->| |
| . .----+<-------| |
| . | | | |
+-----------+----+ +-------------+
A |
| V
+----------------+
| |
| PCS |
| |
+----------------+
A |
| V
Rx Tx
Page 27 excerpt:
"On the transmit side, the PHY will monitor and parse the incoming packet
from the top layer, upon the request of sending IEEE 1588v2 packet, it
will calculate the accurate time of transmission onto the media and a
timestamp accordingly."
Page 28 excerpt:
"On the receive side, the PHY will monitor and parse the incoming packet
from media, and will generate a timestamp upon the reception of IEEE
1588v2 packets. The built-in parser is capable of detecting IEEE 1588v2
on ethernet layer 2 (including untagged, one VLAN tagged and two VLAN
tagged), or layer 3 IPv4/UDP, and IPv6/UDP (including PPPoE and SNAP)."
Thanks for your answers to my questions.
Dave
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