On Thu, Apr 06, 2017 at 01:45:19PM +0200, Axel Holzinger wrote:
> To me it looks like there is trouble correctly adjusting the frequency of
> the PHC, it's always remaining +1000000, but also delays are ridicously high
> and negative (that doesn't make sense, does it?).
Does that SoC use the CPTS? Probably the input clock is wrong. Check
the data sheet and the device tree values for:
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <29>;
Thanks,
Richard
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