> -----Original Message-----
> From: Keller, Jacob E [mailto:jacob.e.kel...@intel.com]
> Sent: Wednesday, August 08, 2018 10:19 AM
> To: Jord Pool <jord.p...@outlook.com>; Richard Cochran
> <richardcoch...@gmail.com>
> Cc: Cliff Spradlin via Linuxptp-users <linuxptp-users@lists.sourceforge.net>; 
> Chris
> Caudle <ch...@chriscaudle.org>; Cliff Spradlin <csprad...@waymo.com>
> Subject: Re: [Linuxptp-users] PXE Boot PTP Issues
> 
> > -----Original Message-----
> > From: Jord Pool [mailto:jord.p...@outlook.com]
> > Sent: Wednesday, August 08, 2018 12:00 AM
> > To: Keller, Jacob E <jacob.e.kel...@intel.com>; Richard Cochran
> > <richardcoch...@gmail.com>
> > Cc: Cliff Spradlin via Linuxptp-users 
> > <linuxptp-users@lists.sourceforge.net>;
> Cliff
> > Spradlin <csprad...@waymo.com>; Chris Caudle <ch...@chriscaudle.org>
> > Subject: Re: PXE Boot PTP Issues

> > After the first timeout indeed more timeouts occur, the offset shoots to 36
> > seconds (always) (which makes me think it makes a mistake in handling the
> > TAI/UTC conversion) and after a while of returning timeout messages the
> offset
> > just drifts away and away (higher offset).
> >
> 
> So, after the first drop, you consistently see more tx timestamp drops? or do
> those go away? If you're still seeing them, then I would expect them to drift
> apart.
> 
> The 36seconds thing I think is a bug in the reset flow of the driver. It's 
> possible
> that something triggers a driver reset, and since the kernel uses the UTC 
> time,
> the driver is resetting to "kernel" time of day, which results in the 
> 36seconds
> offset.
> 
> Thanks,
> Jake
> 


Yea, I double checked the e1000e source, it looks like e1000e_systim_reset is 
using the kernel time to reset the system timer. I suspect this is what causes 
the 36second alignment issue, after it tries to reset to recover...

I don't know what triggers the reset... Maybe the driver should cache the 
current time and restore it after? This does mean that any time lost during the 
reset will be lost, but that's inevitible with a hardware reset that clears the 
register...

Thanks,
Jake

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