Hi, Can you please resolve my following queries. Below are the steps I've followed.
-> I have a FPGA card(PCIe based) on which I've implemented a network driver(on x86, linux) so that ptp4l messages flow to and from the NIC card. -> I have implemented software timestamping. *skb_tx_timestamp()* in the transmit function and *skb_defer_rx_timestamp()* in the bottom half of the receive interrupt handler. -> I'm running my system as a PTP master (two step timestamping, raw ethernet protocol) and connected to a link partner which runs a ptp slave. With the sw timestamping, the slave's offset from master is very high(100s of us). But I need ns level offset. -> To achieve that level of offset accuracy, I think I'll have to implement HW timestamping. -> But then, I have to implement a PHC in my FPGA and add support for that PHC in my linux driver. My query is on the driver side. -> Is it enough if I supply functions to gettime64, settime64 functions of ptp_clock_info structure? -> What functions does ptp4l expect to be implemented in the driver for above said ptp configuration(master,two step timestamp, ethernet protocol) if I use HW timestamping? -> Can you please point me to where exactly the HW timestamping is happening in the ptp4l code? Thanks, Aditya. -- Disclaimer:- This footer text is to convey that this email is sent by one of the users of IITH. So, do not mark it as SPAM.
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