> There is a caveat here : I assume both the ports on the same NIC (mlnx1 and > mlnx2 for example) > have the same hardware clock source even though under /dev/ they are mapped > to different ptp > files i.e /dev/ptp8 and /dev/ptp9 respectively.
Depending on the configuration of the Mellanox NIC, the PHC exposed for different ports will either be the same PHC (in Real-Time Clock mode) - though exposed through two /dev/ files or (in non-Real-Time Clock mode) driver will construct separate PHCs for each of the ports. You can find some instructions on how to configure it here: https://docs.nvidia.com/networking/display/NVIDIA5TTechnologyUserManualv10/Real-Time+Clock And some general documentation on the Real-Time Clock here: https://docs.nvidia.com/networking/display/NVIDIA5TTechnologyUserManualv10/Real+Time+Clock > There are some jitters / unexpected outliers which I attribute to measurement > uncertainties / syscall jitter. 99% of what you're seeing is likely PCIe read latency jitter. This is the reason why phc2sys has the '-N' option to mitigate the problem: > -N phc-num > Specify the number of master clock readings per one slave clock update. > Only the fastest reading is used to update the slave clock, this is useful > to minimize the error caused by random delays in scheduling and bus > utilization. W _______________________________________________ Linuxptp-users mailing list Linuxptp-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/linuxptp-users
