On Mon, Jun 12, 2023 at 12:24:19PM +0800, egg car wrote:
> 5) not only the 4 ports on the same nic, any combination of ptp0~ptp9 results
> the same.
> 
> 
> Have gone through the phc2sys codes, find nothing reasonable that explains
> this issue so far.
> 
> I can see when the large jitter happens, the measured delay also varies a lot,
> perhapse it's related to the pcie tranfication process?

Yes, it's related to PCIe delays. The problem is that the kernel
doesn't provide an ioctl to measure offset between two PHCs, so
phc2sys has to do it in user space using clock_gettime(), which
doesn't work very well (large delay, jitter and asymmetry).

For PHC vs system clock measurements there is an optimized path in the
kernel which for most drivers limits the delay to a single PCIe read.

If you need to synchronize multiple PHCs to each other, it's better to
use one phc2sys instance to synchronize the system clock to the source
PHC and then another phc2sys instance to synchronize the rest of PHCs
to the system clock.

-- 
Miroslav Lichvar



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