From: Pauli Nieminen <[email protected]> Cache flush is required in case CPU is accessing rendered data.
This fixes glean/readPixSanity test case and random rendering errors in sauerbraten and warzone2100. v2 Fix comment ordering in r100_fence_ring_emit and remove extra defines added in first version. Signed-off-by: Pauli Nieminen <[email protected]> Reviewed-by: Jerome Glisse <[email protected]> Signed-off-by: Dave Airlie <[email protected]> drivers/gpu/drm/radeon/r100.c | 10 ++++++++-- 1 files changed, 8 insertions(+), 2 deletions(-) --- http://git.linuxtv.org/v4l-dvb.git?a=commitdiff;h=9e5b2af75abc67c13005c706cf95bbbb78f7fddc diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 11c9a3f..626e790 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -354,11 +354,17 @@ u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) return RREG32(RADEON_CRTC2_CRNT_FRAME); } +/* Who ever call radeon_fence_emit should call ring_lock and ask + * for enough space (today caller are ib schedule and buffer move) */ void r100_fence_ring_emit(struct radeon_device *rdev, struct radeon_fence *fence) { - /* Who ever call radeon_fence_emit should call ring_lock and ask - * for enough space (today caller are ib schedule and buffer move) */ + /* We have to make sure that caches are flushed before + * CPU might read something from VRAM. */ + radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); + radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL); + radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); + radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL); /* Wait until IDLE & CLEAN */ radeon_ring_write(rdev, PACKET0(0x1720, 0)); radeon_ring_write(rdev, (1 << 16) | (1 << 17)); _______________________________________________ linuxtv-commits mailing list [email protected] http://www.linuxtv.org/cgi-bin/mailman/listinfo/linuxtv-commits
