On Thu Jan 8 14:29:46 2026 +0100, Benjamin Gaignard wrote:
> Intra_only frame could be considered as a key frame so Instantaneous
> Decoding Refresh (IDR) flag must be set of the both case and not only
> for key frames.
>
> Signed-off-by: Benjamin Gaignard <[email protected]>
> Reported-by: Jianfeng Liu <[email protected]>
> Fixes: 727a400686a2c ("media: verisilicon: Add Rockchip AV1 decoder")
> Cc: [email protected]
> Reviewed-by: Nicolas Dufresne <[email protected]>
> Signed-off-by: Hans Verkuil <[email protected]>
Patch committed.
Thanks,
Hans Verkuil
drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
---
diff --git a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
index f52b8208e6b9..500e94bcb029 100644
--- a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
+++ b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
@@ -2018,7 +2018,7 @@ static void rockchip_vpu981_av1_dec_set_parameters(struct
hantro_ctx *ctx)
!!(ctrls->frame->quantization.flags
& V4L2_AV1_QUANTIZATION_FLAG_DELTA_Q_PRESENT));
- hantro_reg_write(vpu, &av1_idr_pic_e, !ctrls->frame->frame_type);
+ hantro_reg_write(vpu, &av1_idr_pic_e,
IS_INTRA(ctrls->frame->frame_type));
hantro_reg_write(vpu, &av1_quant_base_qindex,
ctrls->frame->quantization.base_q_idx);
hantro_reg_write(vpu, &av1_bit_depth_y_minus8, ctx->bit_depth - 8);
hantro_reg_write(vpu, &av1_bit_depth_c_minus8, ctx->bit_depth - 8);
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