https://github.com/MkDev11 updated https://github.com/llvm/llvm-project/pull/175262
>From 704f3f099f10aefd96bc5802cf0c5e7975e311da Mon Sep 17 00:00:00 2001 From: mkdev11 <[email protected]> Date: Thu, 15 Jan 2026 02:38:41 +0200 Subject: [PATCH] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 GetRegisterInfo in EmulateInstructionRISCV.cpp was hardcoded to use RegisterInfoPOSIX_riscv64, which caused LLDB to assert when working with RISCV-32 ELF files. This patch adds a check for the architecture and uses RegisterInfoPOSIX_riscv32 when the target is RISCV-32. Fixes #175092 --- .../RISCV/EmulateInstructionRISCV.cpp | 22 +++++++++++++++---- .../Instruction/RISCV/TestRISCVEmulator.cpp | 17 ++++++++++++++ 2 files changed, 35 insertions(+), 4 deletions(-) diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp index 2957cb716041d..960261a83355c 100644 --- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp +++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp @@ -7,6 +7,8 @@ //===----------------------------------------------------------------------===// #include "EmulateInstructionRISCV.h" +#include "Plugins/Process/Utility/RegisterInfoInterface.h" +#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h" #include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h" #include "Plugins/Process/Utility/lldb-riscv-register-enums.h" #include "RISCVCInstructions.h" @@ -1837,10 +1839,22 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind reg_kind, } } - RegisterInfoPOSIX_riscv64 reg_info(m_arch, - RegisterInfoPOSIX_riscv64::eRegsetMaskAll); - const RegisterInfo *array = reg_info.GetRegisterInfo(); - const uint32_t length = reg_info.GetRegisterCount(); + std::unique_ptr<RegisterInfoInterface> reg_info; + switch (m_arch.GetTriple().getArch()) { + case llvm::Triple::riscv32: + reg_info = std::make_unique<RegisterInfoPOSIX_riscv32>( + m_arch, RegisterInfoPOSIX_riscv32::eRegsetMaskAll); + break; + case llvm::Triple::riscv64: + reg_info = std::make_unique<RegisterInfoPOSIX_riscv64>( + m_arch, RegisterInfoPOSIX_riscv64::eRegsetMaskAll); + break; + default: + return {}; + } + + const RegisterInfo *array = reg_info->GetRegisterInfo(); + const uint32_t length = reg_info->GetRegisterCount(); if (reg_index >= length || reg_kind != eRegisterKindLLDB) return {}; diff --git a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp index 90d5a7c4f3b97..f713755c77a7c 100644 --- a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp +++ b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp @@ -16,6 +16,7 @@ #include "lldb/Utility/RegisterValue.h" #include "Plugins/Instruction/RISCV/EmulateInstructionRISCV.h" +#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h" #include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h" #include "Plugins/Process/Utility/lldb-riscv-register-enums.h" @@ -806,3 +807,19 @@ TEST_F(RISCVEmulatorTester, TestFMV_D_XInst) { ASSERT_TRUE(this->Execute(*decode, false)); ASSERT_EQ(this->fpr.fpr[DecodeRD(FMV_D_XInst)], bits); } + +TEST_F(RISCVEmulatorTester, TestGetRegisterInfoRV64) { + // Test that GetRegisterInfo returns valid register info for riscv64. + auto reg_info = this->GetRegisterInfo(eRegisterKindLLDB, gpr_x1_riscv); + ASSERT_TRUE(reg_info.has_value()); + ASSERT_EQ(reg_info->byte_size, 8u); + ASSERT_STREQ(reg_info->name, "ra"); +} + +TEST_F(RISCVEmulatorTester32, TestGetRegisterInfoRV32) { + // Test that GetRegisterInfo returns valid register info for riscv32. + auto reg_info = this->GetRegisterInfo(eRegisterKindLLDB, gpr_x1_riscv); + ASSERT_TRUE(reg_info.has_value()); + ASSERT_EQ(reg_info->byte_size, 4u); + ASSERT_STREQ(reg_info->name, "ra"); +} _______________________________________________ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
