Author: jmolenda
Date: Wed Aug 23 20:22:08 2017
New Revision: 311627

URL: http://llvm.org/viewvc/llvm-project?rev=311627&view=rev
Log:
Change the ftag x87 register from being 8-bits wide to 16-bits wide
to match the changes Saleem Abdulrasool committed in r311579.  Fixes
a testsuite failure now that the testsuite expects a 16 bit return
value for thsi reg.

Modified:
    lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp
    lldb/trunk/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.cpp

Modified: lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp?rev=311627&r1=311626&r2=311627&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp 
(original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp Wed Aug 
23 20:22:08 2017
@@ -1086,7 +1086,7 @@ const DNBRegisterInfo DNBArchImplI386::g
     {e_regSetFPU, fpu_fsw, "fstat", NULL, Uint, Hex, FPU_SIZE_UINT(fsw),
      FPU_OFFSET(fsw), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
      INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
-    {e_regSetFPU, fpu_ftw, "ftag", NULL, Uint, Hex, FPU_SIZE_UINT(ftw),
+    {e_regSetFPU, fpu_ftw, "ftag", NULL, Uint, Hex, 2 /* sizeof __fpu_ftw + 
sizeof __fpu_rsrv1 */,
      FPU_OFFSET(ftw), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
      INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
     {e_regSetFPU, fpu_fop, "fop", NULL, Uint, Hex, FPU_SIZE_UINT(fop),
@@ -1177,7 +1177,7 @@ const DNBRegisterInfo DNBArchImplI386::g
     {e_regSetFPU, fpu_fsw, "fstat", NULL, Uint, Hex, FPU_SIZE_UINT(fsw),
      AVX_OFFSET(fsw), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
      INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
-    {e_regSetFPU, fpu_ftw, "ftag", NULL, Uint, Hex, FPU_SIZE_UINT(ftw),
+    {e_regSetFPU, fpu_ftw, "ftag", NULL, Uint, Hex, 2 /* sizeof __fpu_ftw + 
sizeof __fpu_rsrv1 */,
      AVX_OFFSET(ftw), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
      INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
     {e_regSetFPU, fpu_fop, "fop", NULL, Uint, Hex, FPU_SIZE_UINT(fop),
@@ -1414,7 +1414,7 @@ bool DNBArchImplI386::GetRegisterValue(u
             *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw));
         return true;
       case fpu_ftw:
-        value->value.uint8 = m_state.context.fpu.no_avx.__fpu_ftw;
+        memcpy (&value->value.uint16, &m_state.context.fpu.no_avx.__fpu_ftw, 
2);
         return true;
       case fpu_fop:
         value->value.uint16 = m_state.context.fpu.no_avx.__fpu_fop;
@@ -1607,7 +1607,7 @@ bool DNBArchImplI386::SetRegisterValue(u
         success = true;
         break;
       case fpu_ftw:
-        m_state.context.fpu.no_avx.__fpu_ftw = value->value.uint8;
+        memcpy (&m_state.context.fpu.no_avx.__fpu_ftw, &value->value.uint16, 
2);
         success = true;
         break;
       case fpu_fop:

Modified: 
lldb/trunk/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.cpp?rev=311627&r1=311626&r2=311627&view=diff
==============================================================================
--- lldb/trunk/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.cpp 
(original)
+++ lldb/trunk/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.cpp Wed 
Aug 23 20:22:08 2017
@@ -1380,7 +1380,7 @@ const DNBRegisterInfo DNBArchImplX86_64:
      FPU_OFFSET(fcw), -1U, -1U, -1U, -1U, NULL, NULL},
     {e_regSetFPU, fpu_fsw, "fstat", NULL, Uint, Hex, FPU_SIZE_UINT(fsw),
      FPU_OFFSET(fsw), -1U, -1U, -1U, -1U, NULL, NULL},
-    {e_regSetFPU, fpu_ftw, "ftag", NULL, Uint, Hex, FPU_SIZE_UINT(ftw),
+    {e_regSetFPU, fpu_ftw, "ftag", NULL, Uint, Hex, 2 /* sizeof __fpu_ftw + 
sizeof __fpu_rsrv1 */,
      FPU_OFFSET(ftw), -1U, -1U, -1U, -1U, NULL, NULL},
     {e_regSetFPU, fpu_fop, "fop", NULL, Uint, Hex, FPU_SIZE_UINT(fop),
      FPU_OFFSET(fop), -1U, -1U, -1U, -1U, NULL, NULL},
@@ -1495,7 +1495,7 @@ const DNBRegisterInfo DNBArchImplX86_64:
      AVX_OFFSET(fcw), -1U, -1U, -1U, -1U, NULL, NULL},
     {e_regSetFPU, fpu_fsw, "fstat", NULL, Uint, Hex, FPU_SIZE_UINT(fsw),
      AVX_OFFSET(fsw), -1U, -1U, -1U, -1U, NULL, NULL},
-    {e_regSetFPU, fpu_ftw, "ftag", NULL, Uint, Hex, FPU_SIZE_UINT(ftw),
+    {e_regSetFPU, fpu_ftw, "ftag", NULL, Uint, Hex, 2 /* sizeof __fpu_ftw + 
sizeof __fpu_rsrv1 */,
      AVX_OFFSET(ftw), -1U, -1U, -1U, -1U, NULL, NULL},
     {e_regSetFPU, fpu_fop, "fop", NULL, Uint, Hex, FPU_SIZE_UINT(fop),
      AVX_OFFSET(fop), -1U, -1U, -1U, -1U, NULL, NULL},
@@ -1776,7 +1776,7 @@ bool DNBArchImplX86_64::GetRegisterValue
             *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw));
         return true;
       case fpu_ftw:
-        value->value.uint8 = m_state.context.fpu.no_avx.__fpu_ftw;
+        memcpy (&value->value.uint16, &m_state.context.fpu.no_avx.__fpu_ftw, 
2);
         return true;
       case fpu_fop:
         value->value.uint16 = m_state.context.fpu.no_avx.__fpu_fop;
@@ -1932,7 +1932,7 @@ bool DNBArchImplX86_64::SetRegisterValue
         success = true;
         break;
       case fpu_ftw:
-        m_state.context.fpu.no_avx.__fpu_ftw = value->value.uint8;
+        memcpy (&m_state.context.fpu.no_avx.__fpu_ftw, &value->value.uint8, 2);
         success = true;
         break;
       case fpu_fop:


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